1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to the planarization of a metallization layer and/or the removal of excess metal from a dielectric layer.
2. Description of the Related Art
In manufacturing microstructures, such as integrated circuits, various material layers are deposited on a substrate and are patterned by lithography, such as photolithography, etch processes and the like to provide a large number of individual features such as circuit elements in the form of transistors, capacitors, resistors, interconnect structures and the like. Due to the continuous reduction of feature sizes of the individual structure elements, sophisticated lithography and etch techniques have been developed that allow the resolution of critical dimensions, i.e., of minimum feature sizes, well beyond the wavelength of the radiation used for transferring images from a reticle to a mask layer that is used in subsequent etching processes. Since these sophisticated imaging techniques are quite sensitive to any underlying material layers and to the surface topography, it is frequently necessary to planarize the respective device levels formed above the substrate to provide a substantially planar surface for the application of further material layers to be patterned. This is especially true for so-called metallization layers required in integrated circuits or other microstructure devices comprising a plurality of electric elements to electrically connect the individual circuit elements. Depending on the feature sizes of the circuit elements and the number thereof, a plurality of metallization layers, stacked on top of each other and electrically connected by so-called vias, are typically required for providing the complex functionality of modern integrated circuits.
It has therefore become standard practice in forming stacked metallization layers to planarize the current device level of the substrate prior to forming a subsequent metallization layer. Chemical mechanical polishing (CMP) has proven to be a viable process technique for this purpose. In chemically mechanically polishing a substrate surface, in addition to the mechanical removal of the material, a slurry is supplied, typically containing one or more chemical reagents that react with the material or materials on the surface, wherein the reaction products may then be more efficiently removed by the mechanical polishing process. In addition to the appropriate selection of the slurry composition, the relative motion between the substrate and a polishing pad, as well as the force with which the substrate is pressed against the polishing pad, are controlled to obtain the desired removal rate.
Recently, chemical mechanical polishing has increasingly gained in importance as aluminum is continuously replaced with copper and other metals or metal alloys of enhanced conductivity in high-end integrated circuits exhibiting feature sizes in the deep sub-micron regime. Although copper and alloys thereof exhibit superior characteristics compared to aluminum in terms of conductivity and resistance against electromigration, many problems are involved in processing copper-based materials in a semiconductor facility, one of which resides in the fact that copper may not be very efficiently deposited in large amounts with well-established deposition techniques, such as chemical vapor deposition and sputter deposition. Moreover, copper may not be efficiently patterned by conventional anisotropic etch techniques. Therefore, instead of applying copper or copper alloys as a blanket layer and patterning metal lines, the so-called damascene or in-laid approach has become a standard process technique in forming metallization layers comprised of copper.
In the damascene technique, trenches and vias are formed in a dielectric layer and the metal is subsequently filled into the trenches and vias, wherein a certain amount of over-filling has to be provided to reliably fill the trenches and vias. Prior to depositing the metal, usually by performing a plating process, such as electroplating or electroless plating, a barrier layer is formed in the trench to minimize out-diffusion of copper or other highly diffusive metal compounds into the adjacent dielectric. Thereafter, a thin seed layer for electroplating strategies or any other activation material is usually applied using appropriate deposition techniques, such as sputter deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless deposition and the like, to promote the subsequent plating process of the bulk metal material. After the deposition of the metal, the excess metal, including the thin barrier layer and the seed layer, has to be reliably removed in order to obtain metal trenches and vias that are electrically insulated from each other. The excess material is frequently removed by a process sequence including chemical mechanical polishing. The respective wet chemical deposition process may require sophisticated recipes in order to reliably fill trenches and vias of different aspect ratios in a substantially void-free manner. Moreover, the deposition behavior may depend on the local pattern geometry, that is, densely packed areas may result in a different local deposition rate in areas outside the trenches and vias compared to areas having isolated metal regions. Thus, after the wet chemical deposition process, a pronounced surface topography may be encountered. Due to the complex surface topography and the plurality of different materials that my be present at the same time, at least during a final phase of the polishing process, a sophisticated operation mode may be required for removing the essential amount of the metal in a first polishing period and removing metal, barrier material and to a certain amount the dielectric during a subsequent phase of the polishing process. The polishing process may therefore be carried out in several steps or operation modes, wherein the uniformity of each phase may have a significant influence on the overall process uniformity. Thus, different chemistries in the slurries as well as different parameter settings for the speed of the relative motion and/or the down force applied to the substrate during these different polishing phases may be required. In sophisticated process regimes, the slurries used may have a highly efficient chemical component in order to obtain the desired high removal rate based on the chemical reaction, while abrasives are also added to the slurry to adjust the mechanical removal rate. In the final phase, the removal is more complex as usually two or more materials have to be polished at the same time, i.e., the metal, the barrier material and the dielectric. Moreover, a certain amount of “overpolish” has to be applied in an attempt to remove substantially all of the conductive material on surface portions of the dielectric material to minimize leakage currents or shorts between adjacent metal lines. Completely removing the conductive material from a substrate having a diameter of 200 mm or 300 mm is, however, a challenging task and usually leads to a certain amount of dishing and erosion of the metallization structures, as will be explained with reference to FIGS. 1a and 1b. 
FIG. 1a schematically shows a cross-sectional view of a semiconductor structure 100 including a substrate 101 with a dielectric layer 102 formed above the substrate 101. The substrate 101 may include circuit elements, such as transistors, resistors and the like, which are for convenience not shown in FIG. 1a. The dielectric layer 102 may be comprised of any appropriate material, such as silicon dioxide, silicon nitride, low-k dielectric materials, which are to be understood as dielectrics having a dielectric constant that is approximately 3.0 and less. Trenches 103 having a lateral dimension and a spacing in accordance with device requirements may represent a device area including densely spaced metal lines. For example, the lateral dimensions of the trenches 103 may range from several hundred nanometers to a hundred nanometers and less in sophisticated semiconductor devices. The dielectric layer 102 may further comprise a wide trench 105, which may be provided with increased distance to the densely packed area represented by the trenches 103. The trenches 103 and 105 may be filled with a highly conductive metal 107, such as copper, wherein a respective barrier layer 104 may separate the copper 107 from the dielectric material of the layer 102. The copper layer 107 is formed over the structure 100 with a thickness that reliably fills the trenches 105 and 103, thereby also creating a pronounced surface topography, which may result in an increased excess thickness above the trenches 103 and a minimal excess thickness above the wide trench 105.
The semiconductor structure 100 as shown in FIG. 1a may be formed in accordance with well-known patterning and deposition techniques as already briefly described above. That is, after forming any circuit elements, the dielectric layer 102 may be formed on the basis of well-established techniques, followed by a patterning sequence for forming the trenches 103 and 105. Subsequently, the barrier layer 104 and a seed layer (not shown) may be formed. Next, the copper layer 107 is formed by an electrochemical deposition process, in which usually complex deposition chemistries and current pulse schemes are applied in order to fill the trenches 103 and 105. The local deposition rate may significantly depend on the local pattern density, i.e., the number of metal lines per unit area, the dimension of the openings to be filled and the respective deposition recipe. Hence, significant local height variations of the layer 107 may occur, which may significantly affect a chemical mechanical polishing (CMP) process designed to remove the excess material of the layer 107 and also remove the barrier material of the layer 104 so as to obtain electrically insulated metal lines. During the CMP process, the slurry and the mechanical parameters, such as down force, relative speed between the substrate 101 and a polishing pad and the like, may substantially determine the removal rate and the process uniformity. In sophisticated applications, the removal rate may be enhanced by using a slurry with highly reactive chemical components, while the pronounced surface topography resulting from the deposition of the layer 107 may generate respective height non-uniformities during the CMP process due to the enhanced chemical component of the CMP process.
FIG. 1b schematically shows the semiconductor structure 100 after completion of the CMP process. The conductive materials of the layers 107 and 104 are substantially removed from the surface of the dielectric layer 102. Since respective overpolish times may be required to completely remove any conductive residues between the densely spaced trenches 103 and, due to the enhanced chemical component in the polishing process, a significant degree of dishing 108 may occur, thereby possibly rendering the trench 105 unreliable due to the reduced cross-sectional area that may lead to increased current densities during operation. A reduction of the chemical efficiency of the slurry in favor of an increased mechanical removal component may, however, be less desirable due to a significant reduction of the overall removal rate.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.